On Sun, 23 Mar 2025 13:26:34 +0100 Jernej Škrabec <[email protected]> wrote:
> Dne nedelja, 23. marec 2025 ob 12:35:38 Srednjeevropski standardni čas je > Andre Przywara napisal(a): > > Thanks for Jernej's JTAG debugging effort, it turns out that the BROM > > expects SP_IRQ to be saved and restored, when we want to enter back into > > FEL after the SPL's AArch64 stint. > > Save and restore SP_IRQ as part of the FEL state handling. The banked > > MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was > > introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8 > > cores used in the A10/A13s or older F1C100s SoCs would not support that, > > but this code here is purely in the ARMv8/AArch64 code path, so it's > > safe to use unconditionally. > > > > Reported-by: Jernej Skrabec <[email protected]> > > Signed-off-by: Andre Przywara <[email protected]> > > I have sneaky suspicion that this is already the issue on H616, but I > haven't yet confirmed. That's actually a very good point: if we reset the core, SP_IRQ should be reset as well - on all 64-bit SoCs, so also A64, H5, H6 and H616. We are surely not in an IRQ handler when entering the SPL, so the stack *content* is not relevant, but it should still point to some writable memory. So I keep scratching my head how this worked so far. If I find some time, I will try to dump the SP_IRQ content after reset, on those SoCs. > FWIW: > Reviewed-by: Jernej Skrabec <[email protected]> Thanks for that! Cheers, Andre > > Best regards, > Jernej > > >
