FIXUP! sunxi: mmc: Improve reset procedure

[Andre Przywara]

Hi Jernej,

what do you think about this solution the A10 compilation problem?
That looks like a simple change, somewhat half of the way to the proper
solution.
If you agree, I'd squash that into your patch, then push it for U-Boot
next.

Cheers,
Andre


Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
 drivers/mmc/sunxi_mmc.c | 10 +++++-----
 drivers/mmc/sunxi_mmc.h |  4 ++++
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 31dbfb10c59..951e6acd34d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -449,23 +449,23 @@ out:
        return error;
 }
 
-static void sunxi_mmc_reset(struct sunxi_mmc *regs)
+static void sunxi_mmc_reset(void *regs)
 {
        /* Reset controller */
-       writel(SUNXI_MMC_GCTRL_RESET, &regs->gctrl);
+       writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
        udelay(1000);
 
        if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || 
IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
                /* Reset card */
-               writel(SUNXI_MMC_HWRST_ASSERT, &regs->hwrst);
+               writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
                udelay(10);
-               writel(SUNXI_MMC_HWRST_DEASSERT, &regs->hwrst);
+               writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
                udelay(300);
 
                /* Setup FIFO R/W threshold. Needed on H616. */
                writel(SUNXI_MMC_THLDC_READ_THLD(512) |
                       SUNXI_MMC_THLDC_WRITE_EN |
-                      SUNXI_MMC_THLDC_READ_EN, &regs->thldc);
+                      SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
        }
 }
 
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index 9d55904c213..bc313dcabe0 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -12,6 +12,10 @@
 
 #include <linux/types.h>
 
+#define SUNXI_MMC_GCTRL                0x000
+#define SUNXI_MMC_HWRST                0x078
+#define SUNXI_MMC_THLDC                0x100
+
 struct sunxi_mmc {
        u32 gctrl;              /* 0x00 global control */
        u32 clkcr;              /* 0x04 clock control */
-- 
2.25.1