Hi Andre, On 5/11/25 3:09 AM, Andre Przywara wrote:
From: Cody Eksal <[email protected]>This adds preliminary support for the DRAM controller in the Allwinner A100/A133 SoCs. This is work in progress, and has rough edges, but works on at least three different boards. It contains support for DDR4 and LPDDR4. [Andre: formatting fixes, adapt to mainline, drop unused parameters, remove struct struct sunxi_mctl_com_reg, hardcode MR registers, switch to mctl_check_pattern(), remove simple DRAM check]
Missing Cody's and your Signed-off-by. Cheers, Quentin
