On Sun, May 25, 2025 at 07:05:52PM +0100, Simon Glass wrote: > Hi Tom, > > On Sun, 25 May 2025 at 14:55, Tom Rini <[email protected]> wrote: > > > > On Sun, May 25, 2025 at 09:46:03AM +0100, Simon Glass wrote: > > > > > Hi Tom, > > > > > > It seems that some of the boards in my lab are broken in your tree. > > > Have you noticed that? > > > > Your lab has never fully functioned in mainline, so no I've not paid > > attention to it and don't use it. I figure it's part of the lab > > maintainers duties to figure out false failures and > > more-or-less-expected failures. > > Oh, that's a shame. I didn't know you had stopped using it.
I never used it, since it was never fully green. I thought there was still some problems with the TPM tests for example on one of your platforms. I've only poked it in passing when I needed something specific to your lab. > I use it on nearly every PR. I did once send a patch to disable the > boards that were broken, then another to re-enable them, but I don't > think you took either of them... No, because iirc at least one of your "broken" boards at the time was working I think. > > Here's a recent run showing a few problems: > > https://sjg.u-boot.org/u-boot/u-boot/-/pipelines/794 > > But x86, RISC-V and some rockchip seem to be broken in your tree. I wouldn't characterize any of that as broken, just a combination of lab issues (what Jonas pointed out for rockchip, I don't know when samus last worked in your lab, no idea about zybo) and expected failures (the TPM test, probably an incorrect test on pine64, I forget what the resolution was for vf2). -- Tom
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