On 5/12/25 19:21, Marek Vasut wrote: > Add DT additions required by U-Boot SPL to bring up the hardware. > This includes binman node to generate STM32 Image v2.0 which can be > booted by the BootROM, clock entries used by the SPL clock driver > during clock tree initialization, and syscon-reboot node so U-Boot > can reset the system without having to rely on PSCI call. > > Signed-off-by: Marek Vasut <[email protected]> > --- > Cc: Cheick Traore <[email protected]> > Cc: Fabrice Gasnier <[email protected]> > Cc: Gatien Chevallier <[email protected]> > Cc: Lionel Debieve <[email protected]> > Cc: Pascal Zimmermann <[email protected]> > Cc: Patrice Chotard <[email protected]> > Cc: Patrick Delaunay <[email protected]> > Cc: Simon Glass <[email protected]> > Cc: Sughosh Ganu <[email protected]> > Cc: Tom Rini <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > arch/arm/dts/stm32mp13-u-boot.dtsi | 89 ++++++++++++++++++++++++++++++ > 1 file changed, 89 insertions(+) > > diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi > b/arch/arm/dts/stm32mp13-u-boot.dtsi > index 1fe6966781c..ad63d5027b2 100644 > --- a/arch/arm/dts/stm32mp13-u-boot.dtsi > +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi > @@ -17,6 +17,7 @@ > pinctrl0 = &pinctrl; > }; > > +#if defined(CONFIG_TFABOOT) > firmware { > optee { > bootph-all; > @@ -27,6 +28,86 @@ > psci { > bootph-some-ram; > }; > +#else > + binman: binman { > + multiple-images; > + > + spl-stm32 { > + filename = "u-boot-spl.stm32"; > + mkimage { > + args = "-T stm32imagev2 -a 0x2ffe0000 -e > 0x2ffe0000"; > + u-boot-spl { > + no-write-symbols; > + }; > + }; > + }; > + }; > + > + clocks { > + bootph-all; > + > + clk_hse: ck_hse { > + bootph-all; > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + }; > + > + clk_hsi: ck_hsi { > + bootph-all; > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <64000000>; > + }; > + > + clk_lse: ck_lse { > + bootph-all; > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + }; > + > + clk_lsi: ck_lsi { > + bootph-all; > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + }; > + > + clk_csi: ck_csi { > + bootph-all; > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <4000000>; > + }; > + }; > + > + cpu0_opp_table: cpu0-opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + bootph-pre-ram; > + opp-650000000 { > + bootph-pre-ram; > + opp-hz = /bits/ 64 <650000000>; > + opp-microvolt = <1200000>; > + opp-supported-hw = <0x1>; > + }; > + opp-1000000000 { > + bootph-pre-ram; > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <1350000>; > + opp-supported-hw = <0x2>; > + }; > + }; > + > + reboot { > + bootph-all; > + compatible = "syscon-reboot"; > + regmap = <&rcc>; > + offset = <0x114>; > + mask = <0x1>; > + }; > +#endif > > soc { > bootph-all; > @@ -52,6 +133,14 @@ > bootph-all; > }; > > +#if !defined(CONFIG_TFABOOT) > +&cpu0 { > + nvmem-cells = <&part_number_otp>; > + nvmem-cell-names = "part_number"; > + operating-points-v2 = <&cpu0_opp_table>; > +}; > +#endif > + > &gpioa { > bootph-all; > }; Reviewed-by: Patrice Chotard <[email protected]> Thanks Patrice
