DDR driver of Arria10 SoCFPGA is enhanced in below ways: a) Check DRAM size from device tree and actual hardware, mismatch is notified to the user b) In case DRAM size from device tree is greater than actual hardware, DRAM size is initialized to the hardware value c) Fix a bug during computation of mpu1 address d) Move common code specifically, initializing SDRAM ECC bits to a common sdram_soc32 file. This allows using the same code for future devices. e) DRAM initialization is sped up by enabling Dcache f) Fix hardware watchdog related boot issue
Changes in v3: - Avoid hang if DRAM size from device tree is greater than actual hardware - Correct ECC Scrubbing commit message to appropriate one - Split Dcache patch into two, one explaining hardware watchdog issue in detail - Address minor comments Naresh Kumar Ravulapalli (7): drivers: ddr: altera: Add DRAM size checking for arria10 drivers: ddr: altera: Add valid RAM size check for arria10 drivers: ddr: altera: Fix incorrect address for arria10 mpu1 drivers: ddr: altera: Clean common code for SoC32 devices drivers: ddr: altera: Correct code alignment in sdram file drivers: ddr: altera: Improve DRAM init with Dcache drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram_arria10.c | 112 ++++++++++++++++------------- drivers/ddr/altera/sdram_soc32.c | 88 +++++++++++++++++++++++ drivers/ddr/altera/sdram_soc32.h | 11 +++ 4 files changed, 163 insertions(+), 50 deletions(-) create mode 100644 drivers/ddr/altera/sdram_soc32.c create mode 100644 drivers/ddr/altera/sdram_soc32.h -- 2.35.3
