On Tue Jun 17, 2025 at 7:28 PM IST, Anshul Dalal wrote: > In u-boot we only provide a single MMU table for all k3 platforms, > this does not scale for devices with reserved memory outside the range > 0x9e780000 - 0xa0000000 (eg j722s[1]) or for devices with < 2GiB of > memory (eg am62-SIP with 512MiB of RAM). > > To properly configure the MMU on various k3 platforms, the > reserved-memory regions need to be queried at runtime from the > device-tree and the MMU table should be updated accordingly. > > This patch adds the required fixups to the MMU table (during proper > U-boot stage) by marking the reserved regions as non cacheable and > keeping the remaining area as cacheable. > > For the A-core SPL, the 128MiB region starting from SPL_TEXT_BASE > is marked as cacheable i.e 0x80080000 to 0x88080000. > > The 128MiB size is chosen to allow for future use cases such as falcon > boot from the A-Core SPL which would require loading kernel image from > the SPL stage. This change also ensures the reserved memory regions that > all exist past 0x88080000 are non cacheable preventing speculative > accesses to those addresses. > > [1]: > https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/arm64/arm64-mmu.c?h=ti-u-boot-2025.01-next#n54 > > Signed-off-by: Anshul Dalal <ansh...@ti.com> > --- > Changes for v3: > - Remove unused memory regions in SPL's map > - Add runtime addition of MMU entry for the framebuffer in SPL > - Refactor k3_mem_map_init to use standard u-boot APIs > - Unmap reserved-memory regions instead of keeping them uncached > v2: https://lore.kernel.org/u-boot/20250610160833.1705534-1-ansh...@ti.com/ > > Changes in v2: > - Removed dependency to: > https://lore.kernel.org/u-boot/20250522150941.563959-1-ansh...@ti.com/ > > v1: https://lore.kernel.org/u-boot/20250602120054.1466951-1-ansh...@ti.com/ > ---
[snip] Superseded by v4: https://lore.kernel.org/u-boot/20250618124210.1936140-1-ansh...@ti.com/
