On Fri May 30, 2025 at 6:48 AM -03, Yao Zi wrote: > RISC-V software usually expects that HARTs are running under S mode when > leaving the firmware, for example, the UEFI specification explicitly > states requirements for S mode. > > This series separates M-mode-only code for TH1520 port out, and > configures binman to pack the OpenSBI firmware to initialize the S-mode > environment. Then S-mode proper U-Boot is enabled on our Lichee Pi 4A > port. > > Note that booting on Lichee Pi 4A is broken between PATCH 3 and 4, > affecting bisectability. Considering TH1520 port is still in an early > stage and separating the changes make the commit cleaner, I personally > consider it's acceptable. > > Yao Zi (5): > riscv: cpu: th1520: Build spl.c for SPL only > riscv: cpu: th1520: Support cache enabling/disabling in M mode only > riscv: dts: th1520: Prepare binman configuration for loading OpenSBI > board: thead: licheepi4a: Run proper U-Boot in S-Mode > doc: thead: lpi4a: Update for S-Mode proper U-Boot support > > arch/riscv/cpu/th1520/Makefile | 2 +- > arch/riscv/cpu/th1520/cache.c | 2 + > arch/riscv/dts/thead-th1520-binman.dtsi | 32 +++++- > configs/th1520_lpi4a_defconfig | 1 + > doc/board/thead/lpi4a.rst | 125 +++++++----------------- > 5 files changed, 68 insertions(+), 94 deletions(-)
I also tested with OpenSBI 1.6 on a Lichee Pi 4A 8GB. Tested-by: Ricardo B. Marlière <rica...@marliere.net>
