From: António Silva > > I am trying to activate a PCIe link between two MPC8544 > processor's on a custom board. > One processor is configured as Root Complex > (cfg_host_agt[0:2] = '111') and > the other processor as endpoint (cfg_host_agt[0:2] = '101').
I've done this with many different configurations. > Only PCIe1 is active in both processors (cfg_IO_ports[0:2] = '010') > > In u-boot I set the following flags in both processors: > > #define CONFIG_PCI /* Enable PCI/PCIE */ > #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ //MJ > #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > > In the first processor (configured as RC) I get the following output: > > * pci_init_board: devdisr= 700 0008, io_sel=2, host_agent=7 Fine. > > PCIE1 connected to Slot2 as Root Complex (base address e000a000) > ....PCIE link error. Skipping scan.LTSSM=0x00 As you note below, LTSSM zero is the issue. > PCIE1 on bus 00 - 00* > > In the second processor (configured as EP) I get the following output: > > * pci_init_board: devdisr=7000008, io_sel=2, host_agent=5 > > ** PCIE1 connected to Slot2 as End Point (base address e000a000) > Scanning PCI bus 00 > PCI Scan: Found Bus 0, Device 1, Function 0 > 00 01 1957 0033 0b20 00 The End Point should not scan the bus. Is this old u-boot code? ... > > From the output of the RC processor: > > ....PCIE link error. Skipping scan.LTSSM=0x00 > > from table Table 18-109, the controller doesn't detect any > activity on the bus. It is worse than that, a value of zero indicates the interface is either not wired, in reset, or has no clocks. A value of 8 means the end point's receiver's are detected, but has not trained yet. And 16 is good. Out of reset with no software support, it should go to 8 and then 16 when the end point responds. > I proceed trying to check in the HW for any activity in the > PCIe bus. I don't see any activity in the bus from any of the processors. Both > controller are getting the clock, and apart the PCIe detection both > processor are working an proceed the booting stage. > > Is there any configuration missing in u-boot for the PCIe > configuration? There is a controller reset for an errata workaround (see the setbits 0x08000000 to pdb_stat). But if that was set, I'd expect different symptoms. > > Does anyone has any clue/hint to aid in the debugging process > of the PCIe interface either for the SW and HW side? > > Thanks in advance, > > Antonio > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot