On 6/30/25 02:10, Marek Vasut wrote:
> The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
> to the STM32MP15xx PMIC initialization, except the VTT rail is not
> enabled. Fill in the STM32MP13xx support.
>
> Reviewed-by: Patrice Chotard <[email protected]>
> Signed-off-by: Marek Vasut <[email protected]>
> ---
> Cc: Cheick Traore <[email protected]>
> Cc: Fabrice Gasnier <[email protected]>
> Cc: Gatien Chevallier <[email protected]>
> Cc: Lionel Debieve <[email protected]>
> Cc: Pascal Zimmermann <[email protected]>
> Cc: Patrice Chotard <[email protected]>
> Cc: Patrick Delaunay <[email protected]>
> Cc: Simon Glass <[email protected]>
> Cc: Sughosh Ganu <[email protected]>
> Cc: Tom Rini <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> V2: Add RB from Patrice
> ---
> board/st/common/stpmic1.c | 51 ++++++++++++++++++++++++++-------------
> 1 file changed, 34 insertions(+), 17 deletions(-)
>
> diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
> index 45c2bb5bcea..b46f89dacb9 100644
> --- a/board/st/common/stpmic1.c
> +++ b/board/st/common/stpmic1.c
> @@ -14,8 +14,19 @@
> #include <power/pmic.h>
> #include <power/stpmic1.h>
>
> +static bool is_stm32mp13xx(void)
> +{
> + if (!IS_ENABLED(CONFIG_STM32MP13X))
> + return false;
> +
> + return of_machine_is_compatible("st,stm32mp131") ||
> + of_machine_is_compatible("st,stm32mp133") ||
> + of_machine_is_compatible("st,stm32mp135");
> +}
> +
> int board_ddr_power_init(enum ddr_type ddr_type)
> {
> + bool is_mp13 = is_stm32mp13xx();
> struct udevice *dev;
> bool buck3_at_1800000v = false;
> int ret;
> @@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
> switch (ddr_type) {
> case STM32MP_DDR3:
> /* VTT = Set LDO3 to sync mode */
> - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> - if (ret < 0)
> - return ret;
> -
> - ret &= ~STPMIC1_LDO3_MODE;
> - ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
> -
> - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> - ret);
> - if (ret < 0)
> - return ret;
> + if (!is_mp13) {
> + /* Enable VTT only on STM32MP15xx */
> + ret = pmic_reg_read(dev,
> STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
> + if (ret < 0)
> + return ret;
> +
> + ret &= ~STPMIC1_LDO3_MODE;
> + ret &= ~STPMIC1_LDO12356_VOUT_MASK;
> + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
> +
> + ret = pmic_reg_write(dev,
> STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> + ret);
> + if (ret < 0)
> + return ret;
> + }
>
> /* VDD_DDR = Set BUCK2 to 1.35V */
> ret = pmic_clrsetbits(dev,
> @@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
> mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
>
> /* Enable VTT = LDO3 */
> - ret = pmic_clrsetbits(dev,
> - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> - if (ret < 0)
> - return ret;
> + if (!is_mp13) {
> + /* Enable VTT only on STM32MP15xx */
> + ret = pmic_clrsetbits(dev,
> +
> STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
> + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
> + if (ret < 0)
> + return ret;
> + }
>
> mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
>
Applied to u-boot-stm32/master
Thanks
Patrice
