> -----Original Message----- > From: Ravulapalli, Naresh Kumar <[email protected]> > Sent: Friday, August 8, 2025 5:43 PM > To: [email protected] > Cc: Marek Vasut <[email protected]>; Simon Goldschmidt > <[email protected]>; Chee, Tien Fong > <[email protected]>; Tom Rini <[email protected]>; Ravulapalli, > Naresh Kumar <[email protected]> > Subject: [PATCH] drivers: ddr: altera: Correct DDR calibration status check > > Bit 3 of the seq2core register is no longer set to indicate calibration > completion. Instead, added polling of the seq2core register until it reads > 0b00000111, signaling that the Nios processor has started the calibration > process. > > Signed-off-by: Naresh Kumar Ravulapalli > <[email protected]> > --- > drivers/ddr/altera/sdram_soc64.c | 6 +++--- > drivers/ddr/altera/sdram_soc64.h | 2 +- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/ddr/altera/sdram_soc64.c > b/drivers/ddr/altera/sdram_soc64.c > index 27fbe80ed41..4ce129f5e2b 100644 > --- a/drivers/ddr/altera/sdram_soc64.c > +++ b/drivers/ddr/altera/sdram_soc64.c > @@ -82,11 +82,11 @@ int emif_reset(struct altera_sdram_plat *plat) > debug("DDR: Triggerring emif reset\n"); > hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, > RSTHANDSHAKECTRL); > > - /* if seq2core[3] = 0, we are good */ > + /* if seq2core[2:0] = 0b0000_0111, we are good */ > ret = wait_for_bit_le32((const void *)(plat->hmc + > RSTHANDSHAKESTAT), > - DDR_HMC_SEQ2CORE_INT_RESP_MASK, > - false, 1000, false); > + > DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK, > + true, 1000, false); > if (ret) { > printf("DDR: failed to get ack from EMIF\n"); > return ret; > diff --git a/drivers/ddr/altera/sdram_soc64.h > b/drivers/ddr/altera/sdram_soc64.h > index 183b1a33080..2ed31b99b29 100644 > --- a/drivers/ddr/altera/sdram_soc64.h > +++ b/drivers/ddr/altera/sdram_soc64.h > @@ -64,7 +64,7 @@ struct altera_sdram_plat { > #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) > #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f > #define DDR_HMC_CORE2SEQ_INT_REQ 0xF > -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) > +#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, > 0) > #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f > > #define DDR_HMC_ERRINTEN_INTMASK > \ > -- > 2.35.3 Reviewed-by: Tien Fong Chee <[email protected]> Best regards, Tien Fong
