From: Michael Nazzareno Trimarchi <[email protected]> Sent: Tuesday, 19 August 2025 4:28 pm To: Maniyam, Dinesh <[email protected]> Cc: [email protected]; Marek <[email protected]>; Simon <[email protected]>; Simon Glass <[email protected]>; Tom Rini <[email protected]>; Dario Binacchi <[email protected]>; Chee, Tien Fong <[email protected]>; Hea, Kok Kiang <[email protected]>; Ng, Boon Khai <[email protected]>; Yuslaimi, Alif Zakuan <[email protected]>; Lim, Jit Loon <[email protected]>; Dinesh Maniyam <[email protected]> Subject: Re: [PATCH v2] mtd: nand: cadence: Fix device assignment to avoid warm reset issue
[CAUTION: This email is from outside your organization. Unless you trust the sender, do not click on links or open attachments as it may be a fraudulent email attempting to steal your information and/or compromise your computer.] Hi Dinesh Please adjust your signature seems that intel.com<http://intel.com> domain is not valid Michael Hi, Submitted v3. Signature adjusted. Thanks! On Tue, Aug 19, 2025 at 10:23 AM Michael Nazzareno Trimarchi <[email protected]<mailto:[email protected]>> wrote: On Tue, Aug 19, 2025 at 9:16 AM <[email protected]<mailto:[email protected]>> wrote: From: Dinesh Maniyam <[email protected]<mailto:[email protected]>> The driver currently does: mtd->dev->parent = cadence->dev; This works in Linux because `struct mtd_info` embeds a `struct device`, so `mtd->dev` is always valid and its `.parent` can be set. In U-Boot, however, `mtd->dev` is only a pointer to a `struct udevice`. Dereferencing it before assignment is invalid, which breaks the device hierarchy. As a result, consumers relying on `mtd->dev` (e.g. partition parser, reset and re-init paths) operate on a dangling pointer. This leads to failures during warm reset when the NAND device is accessed again. Fix by assigning the device pointer directly: mtd->dev = cadence->dev; This matches U-Boot’s device model, preserves a valid hierarchy, and resolves the warm reset issue on Cadence NAND. Fixes: ebc41cad ("drivers: mtd: nand: Add driver for Cadence Nand") Signed-off-by: Dinesh Maniyam <[email protected]<mailto:[email protected]>> --- Reviewed-by: Michael Trimarchi <[email protected]<mailto:[email protected]>> drivers/mtd/nand/raw/cadence_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c index 27aa7f97a45..4771440d1de 100644 --- a/drivers/mtd/nand/raw/cadence_nand.c +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -2196,7 +2196,7 @@ static int cadence_nand_chip_init(struct cadence_nand_info *cadence, ofnode node chip->controller = &cadence->controller; nand_set_flash_node(chip, node); mtd = nand_to_mtd(chip); - mtd->dev->parent = cadence->dev; + mtd->dev = cadence->dev; chip->options |= NAND_BUSWIDTH_AUTO; chip->select_chip = cadence_nand_select_chip; -- 2.35.3 -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 [email protected]<mailto:[email protected]> __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 [email protected]<mailto:[email protected]> www.amarulasolutions.com<http://www.amarulasolutions.com> -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 [email protected]<mailto:[email protected]> __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 [email protected]<mailto:[email protected]> www.amarulasolutions.com<http://www.amarulasolutions.com>
