The documentation for the UART controller in the APQ8016E specifies that both RESET and ENABLE commands must be issued to set up the receiver and transmitter, but at the moment we only issue RESET. This doesn't seem to cause issues in practice (looks like the reset already re-enables the receiver/transmitter), but let's add the two writes to RX_ENABLE/TX_ENABLE to better match the recommendations in the documentation.
Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> --- drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 5523ec4afe17f242d61bc2ec4b4534b5b974434c..2c08a84b02773663f3c3a11eddaaa7a8bab2b4a1 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -50,6 +50,8 @@ #define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */ #define UARTDM_CR 0xA8 /* Command register */ +#define UARTDM_CR_RX_ENABLE (1 << 0) /* Enable receiver */ +#define UARTDM_CR_TX_ENABLE (1 << 2) /* Enable transmitter */ #define UARTDM_CR_CMD_RESET_RX (1 << 4) /* Reset receiver */ #define UARTDM_CR_CMD_RESET_TX (2 << 4) /* Reset transmitter */ #define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */ @@ -225,6 +227,8 @@ static void uart_dm_init(struct msm_serial_data *priv) writel(UARTDM_CR_CMD_RESET_RX, priv->base + UARTDM_CR); writel(UARTDM_CR_CMD_RESET_TX, priv->base + UARTDM_CR); + writel(UARTDM_CR_RX_ENABLE, priv->base + UARTDM_CR); + writel(UARTDM_CR_TX_ENABLE, priv->base + UARTDM_CR); } static int msm_serial_probe(struct udevice *dev) { -- 2.50.1
