If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at arch/arm/cpu/armv8/start.S.
Signed-off-by: Kunihiko Hayashi <[email protected]> --- include/configs/qemu-sbsa.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h index aff78160e12a..669d0fe7c58b 100644 --- a/include/configs/qemu-sbsa.h +++ b/include/configs/qemu-sbsa.h @@ -86,4 +86,8 @@ #define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE 0x1000000 +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR +#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR + #endif /* __CONFIG_H */ -- 2.34.1
