Hi all, In U-Boot, TI only provides a single memory map for all k3 platforms, this does not scale for devices where atf and optee lie outside the range 0x80000000 - 0x80080000 and 0x9e780000 - 0xa0000000 respectively.
There are also issues for devices with < 2GiB of memory (eg am62SiP with 512MiB of RAM) as the maximum size for the first DRAM bank is hardcoded to 2GiB. Furthermore the second DRAM bank is mapped even for devices that only have one. Therefore this patch set adds the required functionality to create the MMU table at runtime. The patch set has been build tested on all effected platforms but boot-tested only on TI's K3 EVMs, the beagleplay and phytec's phycore-am6* platforms. The following effected boards have not been boot tested: - verdin-am62 - iot2050 Depends on: [PATCH v1] mach-k3: fix reading size and addr from fdt on R5 https://lore.kernel.org/u-boot/[email protected]/ Best Wishes, Anshul --- Changes in v7: - Pick up R-by and Tested-by tags - Use nobreak API for unmapping MMU region - Better error messages and minor refactor v6: https://lore.kernel.org/u-boot/[email protected]/ Changes in v6: - Make use of generic MMU APIs - Extend core U-Boot functionality by adding mmu_unmap_reserved_mem and mem_map_fix_dram_banks - Keep same memory maps for SPL and U-Boot proper - Add fdt fixups from SPL stage for reserved memory nodes v5: https://lore.kernel.org/u-boot/[email protected]/ Changes in v5: - Don't create carveouts for every reserved-memory node - Only create carveouts for ATF/OP-TEE - Expand the call to k3_mem_map_init to vendor boards as well - Map area for framebuffer for CONFIG_VIDEO=y platforms v4: https://lore.kernel.org/u-boot/[email protected]/ Changes for v4: - Add call to k3_mem_map_init for beagleplay - Mark reserved regions as non-cacheable - More debug logs v3: https://lore.kernel.org/u-boot/[email protected]/ Changes for v3: - Remove unused memory regions in SPL's map - Add runtime addition of MMU entry for the framebuffer in SPL - Refactor k3_mem_map_init to use standard u-boot APIs - Unmap reserved-memory regions instead of keeping them uncached v2: https://lore.kernel.org/u-boot/[email protected]/ Changes in v2: - Removed dependency to: https://lore.kernel.org/u-boot/[email protected]/ v1: https://lore.kernel.org/u-boot/[email protected]/ --- Anshul Dalal (10): mach-k3: use minimal memory map for all K3 mach-k3: use custom enable_cache arm: armv8: mmu: export mmu_setup arm: armv8: invalidate dcache entries on dcache_enable arm: armv8: mmu: add mem_map_fix_dram_banks mach-k3: map all banks using mem_map_fix_dram_banks arm: armv8: mmu: add mmu_unmap_reserved_mem spl: split spl_board_fixups to arch/board specific mach-k3: add reserved memory fixups for next boot stage mach-k3: add carveouts for TFA and optee arch/arm/cpu/armv7m/cpu.c | 2 +- arch/arm/cpu/armv8/cache_v8.c | 58 ++++++++++++++++++++-- arch/arm/include/asm/armv8/mmu.h | 24 +++++++++ arch/arm/mach-k3/arm64/arm64-mmu.c | 35 +++++-------- arch/arm/mach-k3/common.c | 55 ++++++++++++++++++++ arch/arm/mach-k3/include/mach/k3-ddr.h | 6 +++ arch/arm/mach-rockchip/spl-boot-order.c | 2 +- arch/arm/mach-socfpga/spl_soc64.c | 2 +- board/beagle/beagley-ai/beagley-ai.c | 2 +- board/dhelectronics/dh_stm32mp1/board.c | 2 +- board/phytec/phycore_am62x/phycore-am62x.c | 2 +- board/phytec/phycore_am64x/phycore-am64x.c | 2 +- board/renesas/sparrowhawk/sparrowhawk.c | 2 +- board/starfive/visionfive2/spl.c | 2 +- board/ti/am62ax/evm.c | 2 +- board/ti/am62px/evm.c | 2 +- board/ti/am62x/evm.c | 2 +- board/ti/am64x/evm.c | 2 +- board/ti/j721e/evm.c | 2 +- board/ti/j721s2/evm.c | 2 +- board/ti/j722s/evm.c | 2 +- board/ti/j784s4/evm.c | 2 +- common/spl/spl.c | 12 +++-- include/spl.h | 12 +++-- 24 files changed, 186 insertions(+), 50 deletions(-) -- 2.51.0
