> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <[email protected]>
> Sent: Thursday, 11 September, 2025 1:21 PM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Simon Goldschmidt
> <[email protected]>; Chee, Tien Fong
> <[email protected]>; Tom Rini <[email protected]>; Ravulapalli,
> Naresh Kumar <[email protected]>
> Subject: [PATCH v3 1/2] drivers: clk: agilex: Fix EMAC clock source selection
>
> Fix the incorrect bit masking and bit shift used to compute EMAC control which
> in turn is used to select EMAC clock from EMAC source A or B.
>
> Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
> ---
> drivers/clk/altera/clk-agilex.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/altera/clk-agilex.c
> b/drivers/clk/altera/clk-agilex.c index
> 242740a4b00..16a37b962cd 100644
> --- a/drivers/clk/altera/clk-agilex.c
> +++ b/drivers/clk/altera/clk-agilex.c
> @@ -544,14 +544,14 @@ static u32 clk_get_emac_clk_hz(struct
> socfpga_clk_plat *plat, u32 emac_id)
> /* Get EMAC clock source */
> ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
> if (emac_id == AGILEX_EMAC0_CLK)
> - ctl = (ctl >>
> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
> - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
> + ctl = (ctl &
> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >>
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET;
> else if (emac_id == AGILEX_EMAC1_CLK)
> - ctl = (ctl >>
> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
> - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
> + ctl = (ctl &
> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >>
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET;
> else if (emac_id == AGILEX_EMAC2_CLK)
> - ctl = (ctl >>
> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
> - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
> + ctl = (ctl &
> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >>
> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET;
> else
> return 0;
>
> --
> 2.35.3
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
