Add ACR in all PLL setting. Add correct ACR value for each PLL used in different SoCs.
Signed-off-by: Manikandan Muralidharan <[email protected]> Signed-off-by: Varshini Rajendran <[email protected]> --- drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 2 ++ drivers/clk/at91/sam9x7.c | 5 +++++ drivers/clk/at91/sama7d65.c | 1 + drivers/clk/at91/sama7g5.c | 1 + 5 files changed, 10 insertions(+) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 580c9964ff4..f38868d1665 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -42,6 +42,7 @@ struct clk_pll_characteristics { u16 *icpll; u8 *out; u8 upll : 1; + u32 acr; }; struct clk_pll_layout { diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e04266a2be2..2251e2846fa 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -123,6 +123,7 @@ static const struct clk_pll_characteristics apll_characteristics = { .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .core_output = core_outputs, + .acr = 0x00020010UL, }; static const struct clk_pll_characteristics upll_characteristics = { @@ -131,6 +132,7 @@ static const struct clk_pll_characteristics upll_characteristics = { .output = upll_outputs, .core_output = core_outputs, .upll = true, + .acr = 0x12023010UL, /* fIN = [18 MHz, 32 MHz]*/ }; /* Layout for fractional PLLs. */ diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index ad9865feff0..9ea253e6ff8 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -164,6 +164,7 @@ static const struct clk_pll_characteristics plla_characteristics = { .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .core_output = plla_core_outputs, + .acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */ }; static const struct clk_pll_characteristics upll_characteristics = { @@ -172,6 +173,7 @@ static const struct clk_pll_characteristics upll_characteristics = { .output = upll_outputs, .core_output = upll_core_outputs, .upll = true, + .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */ }; static const struct clk_pll_characteristics lvdspll_characteristics = { @@ -179,6 +181,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = { .num_output = ARRAY_SIZE(lvdspll_outputs), .output = lvdspll_outputs, .core_output = lvdspll_core_outputs, + .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */ }; static const struct clk_pll_characteristics audiopll_characteristics = { @@ -186,6 +189,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = { .num_output = ARRAY_SIZE(audiopll_outputs), .output = audiopll_outputs, .core_output = audiopll_core_outputs, + .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */ }; static const struct clk_pll_characteristics plladiv2_characteristics = { @@ -193,6 +197,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = { .num_output = ARRAY_SIZE(plladiv2_outputs), .output = plladiv2_outputs, .core_output = plladiv2_core_outputs, + .acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */ }; /* Layout for fractional PLLs. */ diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 8d2c25e6fa9..9f0b394543b 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -184,6 +184,7 @@ static const struct clk_pll_characteristics pll_characteristics = { .num_output = ARRAY_SIZE(pll_outputs), .output = pll_outputs, .core_output = core_outputs, + .acr = 0x00070010UL, }; /* Layout for fractional PLLs. */ diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index c0e27828b1a..f24d251857f 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -169,6 +169,7 @@ static const struct clk_pll_characteristics pll_characteristics = { .num_output = ARRAY_SIZE(pll_outputs), .output = pll_outputs, .core_output = core_outputs, + .acr = 0x00070010UL, }; /* Layout for fractional PLLs. */ -- 2.25.1
