Add PCIE1 and PCIE2 ECAM space and outbound space to MMU pagetable, so A55 can access them.
Signed-off-by: Ye Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> --- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index f973652d0cb..aa4702f3b6f 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -254,6 +254,30 @@ static struct mm_region imx9_mem_map[] = { PTE_BLOCK_OUTER_SHARE }, { #endif + /* PCIE2 ECAM */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE1 Outbound */ + .virt = 0x900000000UL, + .phys = 0x900000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE2 Outbound */ + .virt = 0xA00000000UL, + .phys = 0xA00000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, }, { -- 2.37.1
