Add JH7110 SoC DDR external memory controller.
Signed-off-by: E Shattow <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
[ upstream commit: 7114969021ec5c4c0f3df1da3a8790f75dda92e2 ]
(cherry picked from commit 8d5c520b73b7c29b714f75e99ed48baa55fc5fa1)
---
dts/upstream/src/riscv/starfive/jh7110.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi
b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index 0ba74ef0467..f3876660c07 100644
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -931,6 +931,18 @@
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
+ memory-controller@15700000 {
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x15700000 0x0 0x10000>,
+ <0x0 0x13000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+ clock-names = "pll";
+ resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+ <&syscrg JH7110_SYSRST_DDR_OSC>,
+ <&syscrg JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ };
+
crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;
--
2.50.0
