On 2025/10/19 23:47, Jonas Karlman wrote:
From: Jon Lin <[email protected]>
SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.
Signed-off-by: Jon Lin <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Thanks,
- Kever
---
v4: No change
v3: No change
v2: No change
---
drivers/spi/rockchip_sfc.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index 73738ab26d33..60e74117057a 100644
--- a/drivers/spi/rockchip_sfc.c
+++ b/drivers/spi/rockchip_sfc.c
@@ -108,6 +108,7 @@
#define SFC_VER_3 0x3
#define SFC_VER_4 0x4
#define SFC_VER_5 0x5
+#define SFC_VER_8 0x8
/* Delay line controller resiter */
#define SFC_DLL_CTRL0 0x3C
@@ -589,6 +590,16 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave
*mem, struct spi_mem_op
return 0;
}
+#if CONFIG_IS_ENABLED(CLK)
+static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, uint speed)
+{
+ if (sfc->version >= SFC_VER_8)
+ return clk_set_rate(&sfc->clk, speed * 2);
+ else
+ return clk_set_rate(&sfc->clk, speed);
+}
+#endif
+
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
{
struct rockchip_sfc *sfc = dev_get_plat(bus);
@@ -600,7 +611,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus, uint
speed)
return 0;
#if CONFIG_IS_ENABLED(CLK)
- int ret = clk_set_rate(&sfc->clk, speed);
+ int ret = rockchip_sfc_clk_set_rate(sfc, speed);
if (ret < 0) {
dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support
level\n",
--
Thanks & Best regards,
Kever Yang
**************************************************************************************************
杨凯 市场部 Kever Yang Marketing Department
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