On 10/31/2025 11:04 AM, Neha Malcom Francis wrote:
Update the DDR configuration for J742S2 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Signed-off-by: Neha Malcom Francis <[email protected]> --- arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi | 4872 +----------------- 1 file changed, 263 insertions(+), 4609 deletions(-) diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi index a64d19b05f3..2cd21efbf93 100644 --- a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 15:02:20 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/
For whole Series Tested-by: Udit Kumar <[email protected]>
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