Refresh format using clang-format.
Signed-off-by: Beiyan Yun <[email protected]>
---
Changes in v4:
- New
drivers/net/phy/aquantia.c | 159 +++++++++++++++++--------------------
1 file changed, 75 insertions(+), 84 deletions(-)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 903fcd667f6..439c4c48bdc 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -18,28 +18,28 @@
#include <asm/byteorder.h>
#include <fs.h>
-#define AQUNTIA_10G_CTL 0x20
-#define AQUNTIA_VENDOR_P1 0xc400
+#define AQUNTIA_10G_CTL 0x20
+#define AQUNTIA_VENDOR_P1 0xc400
-#define AQUNTIA_SPEED_LSB_MASK 0x2000
-#define AQUNTIA_SPEED_MSB_MASK 0x40
+#define AQUNTIA_SPEED_LSB_MASK 0x2000
+#define AQUNTIA_SPEED_MSB_MASK 0x40
-#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
-#define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
+#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
+#define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
-#define AQUANTIA_FIRMWARE_ID 0x20
-#define AQUANTIA_RESERVED_STATUS 0xc885
-#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
-#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
-#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
+#define AQUANTIA_FIRMWARE_ID 0x20
+#define AQUANTIA_RESERVED_STATUS 0xc885
+#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
+#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
+#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
-#define AQUANTIA_SI_IN_USE_MASK 0x0078
-#define AQUANTIA_SI_USXGMII 0x0018
+#define AQUANTIA_SI_IN_USE_MASK 0x0078
+#define AQUANTIA_SI_USXGMII 0x0018
/* registers in MDIO_MMD_VEND1 region */
-#define AQUANTIA_VND1_GLOBAL_SC 0x000
-#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
+#define AQUANTIA_VND1_GLOBAL_SC 0x000
+#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
#define GLOBAL_FIRMWARE_ID 0x20
#define GLOBAL_FAULT 0xc850
@@ -71,35 +71,35 @@
#define UP_RUN_STALL_OVERRIDE BIT(6)
#define UP_RUN_STALL BIT(0)
-#define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
-#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
+#define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
/* MDI reversal configured through registers */
-#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
/* MDI reversal enabled */
-#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
/*
* global start rate, the protocol associated with this speed is used by
default
* on SI.
*/
-#define AQUANTIA_VND1_GSTART_RATE 0x31a
-#define AQUANTIA_VND1_GSTART_RATE_OFF 0
-#define AQUANTIA_VND1_GSTART_RATE_100M 1
-#define AQUANTIA_VND1_GSTART_RATE_1G 2
-#define AQUANTIA_VND1_GSTART_RATE_10G 3
-#define AQUANTIA_VND1_GSTART_RATE_2_5G 4
-#define AQUANTIA_VND1_GSTART_RATE_5G 5
+#define AQUANTIA_VND1_GSTART_RATE 0x31a
+#define AQUANTIA_VND1_GSTART_RATE_OFF 0
+#define AQUANTIA_VND1_GSTART_RATE_100M 1
+#define AQUANTIA_VND1_GSTART_RATE_1G 2
+#define AQUANTIA_VND1_GSTART_RATE_10G 3
+#define AQUANTIA_VND1_GSTART_RATE_2_5G 4
+#define AQUANTIA_VND1_GSTART_RATE_5G 5
/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
-#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
-#define AQUANTIA_VND1_GSYSCFG_100M 0
-#define AQUANTIA_VND1_GSYSCFG_1G 1
-#define AQUANTIA_VND1_GSYSCFG_2_5G 2
-#define AQUANTIA_VND1_GSYSCFG_5G 3
-#define AQUANTIA_VND1_GSYSCFG_10G 4
+#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
+#define AQUANTIA_VND1_GSYSCFG_100M 0
+#define AQUANTIA_VND1_GSYSCFG_1G 1
+#define AQUANTIA_VND1_GSYSCFG_2_5G 2
+#define AQUANTIA_VND1_GSYSCFG_5G 3
+#define AQUANTIA_VND1_GSYSCFG_10G 4
-#define AQUANTIA_VND1_SMBUS0 0xc485
-#define AQUANTIA_VND1_SMBUS1 0xc495
+#define AQUANTIA_VND1_SMBUS0 0xc485
+#define AQUANTIA_VND1_SMBUS1 0xc495
/* addresses of memory segments in the phy */
#define DRAM_BASE_ADDR 0x3FFE0000
@@ -111,10 +111,10 @@
#define HEADER_OFFSET 0x300
/* driver private data */
-#define AQUANTIA_NA 0
-#define AQUANTIA_GEN1 1
-#define AQUANTIA_GEN2 2
-#define AQUANTIA_GEN3 3
+#define AQUANTIA_NA 0
+#define AQUANTIA_GEN1 1
+#define AQUANTIA_GEN2 2
+#define AQUANTIA_GEN3 3
#pragma pack(1)
struct fw_header {
@@ -168,8 +168,8 @@ static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
cleanup:
if (ret < 0) {
printf("loading firmware file %s %s failed with error %d\n",
- CONFIG_PHY_AQUANTIA_FW_PART,
- CONFIG_PHY_AQUANTIA_FW_NAME, ret);
+ CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME,
+ ret);
free(addr);
}
return ret;
@@ -232,7 +232,7 @@ static int aquantia_upload_firmware(struct phy_device
*phydev)
if (ret != 0)
return ret;
- read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
+ read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
if (read_crc != calculated_crc) {
printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
@@ -257,21 +257,22 @@ static int aquantia_upload_firmware(struct phy_device
*phydev)
strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
VERSION_STRING_SIZE);
- printf("%s loading firmware version '%s'\n", phydev->dev->name,
version);
+ printf("%s loading firmware version '%s'\n", phydev->dev->name,
+ version);
/* stall the microcprocessor */
phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
- debug("loading dram 0x%08x from offset=%d size=%d\n",
- DRAM_BASE_ADDR, dram_offset, dram_size);
+ debug("loading dram 0x%08x from offset=%d size=%d\n", DRAM_BASE_ADDR,
+ dram_offset, dram_size);
ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
dram_size);
if (ret != 0)
goto done;
- debug("loading iram 0x%08x from offset=%d size=%d\n",
- IRAM_BASE_ADDR, iram_offset, iram_size);
+ debug("loading iram 0x%08x from offset=%d size=%d\n", IRAM_BASE_ADDR,
+ iram_offset, iram_size);
ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
iram_size);
if (ret != 0)
@@ -306,14 +307,14 @@ struct {
int cnt;
u16 start_rate;
} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
- [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
- AQUANTIA_VND1_GSTART_RATE_1G},
- [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
- AQUANTIA_VND1_GSTART_RATE_2_5G},
- [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
- AQUANTIA_VND1_GSTART_RATE_10G},
- [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
- AQUANTIA_VND1_GSTART_RATE_10G},
+ [PHY_INTERFACE_MODE_SGMII] = { 0x04b, AQUANTIA_VND1_GSYSCFG_1G,
+ AQUANTIA_VND1_GSTART_RATE_1G },
+ [PHY_INTERFACE_MODE_2500BASEX] = { 0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
+ AQUANTIA_VND1_GSTART_RATE_2_5G },
+ [PHY_INTERFACE_MODE_10GBASER] = { 0x100, AQUANTIA_VND1_GSYSCFG_10G,
+ AQUANTIA_VND1_GSTART_RATE_10G },
+ [PHY_INTERFACE_MODE_USXGMII] = { 0x080, AQUANTIA_VND1_GSYSCFG_10G,
+ AQUANTIA_VND1_GSTART_RATE_10G },
};
static int aquantia_set_proto(struct phy_device *phydev,
@@ -352,8 +353,8 @@ static int aquantia_dts_config(struct phy_device *phydev)
if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
debug("mdi-reversal = %d\n", (int)prop);
- reg = phy_read(phydev, MDIO_MMD_PMAPMD,
- AQUANTIA_PMA_RX_VENDOR_P1);
+ reg = phy_read(phydev, MDIO_MMD_PMAPMD,
+ AQUANTIA_PMA_RX_VENDOR_P1);
reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
@@ -501,11 +502,11 @@ int aquantia_config(struct phy_device *phydev)
!(val & AQUNTIA_SPEED_MSB_MASK))
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
AQUNTIA_SPEED_LSB_MASK |
- AQUNTIA_SPEED_MSB_MASK);
+ AQUNTIA_SPEED_MSB_MASK);
/* If SI is USXGMII then start USXGMII autoneg */
- reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
- AQUANTIA_VENDOR_PROVISIONING_REG);
+ reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_VENDOR_PROVISIONING_REG);
if (usx_an) {
reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
@@ -542,8 +543,7 @@ int aquantia_config(struct phy_device *phydev)
reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
- phydev->drv->name,
- (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
+ phydev->drv->name, (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
(val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
@@ -604,9 +604,8 @@ U_BOOT_PHY_DRIVER(aq1202) = {
.uid = 0x3a1b445,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
- MDIO_MMD_VEND1),
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
@@ -617,9 +616,8 @@ U_BOOT_PHY_DRIVER(aq2104) = {
.uid = 0x3a1b460,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
- MDIO_MMD_VEND1),
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
@@ -630,9 +628,8 @@ U_BOOT_PHY_DRIVER(aqr105) = {
.uid = 0x3a1b4a2,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
- MDIO_MMD_VEND1),
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
@@ -644,9 +641,8 @@ U_BOOT_PHY_DRIVER(aqr106) = {
.uid = 0x3a1b4d0,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
- MDIO_MMD_VEND1),
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
@@ -657,9 +653,8 @@ U_BOOT_PHY_DRIVER(aqr107) = {
.uid = 0x3a1b4e0,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
- MDIO_MMD_VEND1),
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
@@ -671,8 +666,7 @@ U_BOOT_PHY_DRIVER(aqr112) = {
.uid = 0x3a1b660,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
@@ -685,8 +679,7 @@ U_BOOT_PHY_DRIVER(aqr113c) = {
.uid = 0x31c31c12,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
@@ -699,8 +692,7 @@ U_BOOT_PHY_DRIVER(aqr405) = {
.uid = 0x3a1b4b2,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
@@ -713,8 +705,7 @@ U_BOOT_PHY_DRIVER(aqr412) = {
.uid = 0x3a1b710,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
- .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
- MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
--
2.47.3
