This series adds PCIe endpoint boot support for the TI J784S4 SoC. PCIe boot allows the device to boot as a PCIe endpoint, where the bootloader images are loaded by a PCIe host through Device Firmware Upgrade (DFU) over PCIe.
The J784S4 SoC uses PCIe1 instance with SERDES0 for endpoint boot. To enable this functionality, the SERDES and PCIe peripherals must be configured early in the R5 SPL stage before the bootloader images can be transferred from the host. This series: 1. Adds the required clock and device data for SERDES0 and PCIe1 2. Enables Cadence Torrent PHY driver at SPL stage 3. Enables J721E WIZ SERDES wrapper driver at SPL stage 4. Enables PCIe boot configs for R5 and A72 stage This feature has been tested on J784S4 EVM. Following are the logs corresponding to this feature. https://gist.github.com/hrushikesh221/cf48b512eb4cd90c1612ad2e531b8ffe Program used to copy bootloaders from PCIe Root-Complex to Endpoint: https://gist.github.com/hrushikesh221/94e6042dbd717c74b74a5c9fc8ec5b6c This series is based on commit : 6b27b688694 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh Hrushikesh Salunke (5): arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot arch/arm/mach-k3/r5/j784s4/clk-data.c | 211 ++++++++++++++++++++++++-- arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 +++--- configs/j784s4_evm_a72_defconfig | 7 + configs/j784s4_evm_r5_defconfig | 13 ++ drivers/phy/cadence/Kconfig | 7 + drivers/phy/ti/Kconfig | 10 ++ 6 files changed, 264 insertions(+), 29 deletions(-) -- 2.34.1
