在 2025/11/14 星期五 12:41, Geraldo Nascimento 写道:
On Wed, Nov 12, 2025 at 10:09:15PM -0300, Geraldo Nascimento wrote:
Hi Ye, Shawn,
Here's more contained workaround without resorting to clearing DDR to
INPUT for every GPIO:
diff --git a/drivers/pci/controller/pcie-rockchip-host.c
b/drivers/pci/controller/pcie-rockchip-host.c
index ee1822ca01db..1d89131ec6ac 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -315,7 +315,8 @@ static int rockchip_pcie_host_init_port(struct
rockchip_pcie *rockchip)
PCIE_CLIENT_CONFIG);
msleep(PCIE_T_PVPERL_MS);
- gpiod_set_value_cansleep(rockchip->perst_gpio, 1);
+ gpiod_direction_input(rockchip->perst_gpio);
+ gpiod_direction_output(rockchip->perst_gpio, 1);
msleep(PCIE_RESET_CONFIG_WAIT_MS);
This results in working PCIe for me, pass initial link training.
Sorry for the inconvenience of more mail, but I'm providing as much
detail as I can.
Don't worry, it's helpful, so I think Ye could have a look.
May I ask if the failure only happened to one specific board?
Another thing I noticed is about one commit:
114b06ee108c ("PCI: rockchip: Set Target Link Speed to 5.0 GT/s before
retraining")
It said: "Rockchip controllers can support up to 5.0 GT/s link speed."
But we issued an errata long time ago to announced it doesn't, you could
also check the PCIe part of RK3399 datasheet:
https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf
Also we set max-link-speed to ONE in rk3399-base.dtsi but seems another
patch slip in: 755fff528b1b ("arm64: dts: rockchip: add variables for
pcie completion to helios64")
This hack has been confirmed to work in U-boot also.
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 19f9e58a640..5702b607ee6 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -329,8 +329,10 @@ static int rockchip_pcie_init_port(struct udevice *dev)
writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
priv->apb_base + PCIE_CLIENT_CONFIG);
- if (dm_gpio_is_valid(&priv->ep_gpio))
- dm_gpio_set_value(&priv->ep_gpio, 1);
+ if (dm_gpio_is_valid(&priv->ep_gpio)) {
+ dm_gpio_set_dir_flags(&priv->ep_gpio, (priv->ep_gpio.flags &
~GPIOD_IS_OUT) | GPIOD_IS_IN);
+ dm_gpio_set_dir_flags(&priv->ep_gpio, (priv->ep_gpio.flags &
~GPIOD_IS_IN) | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
ret = readl_poll_sleep_timeout
(priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,
So my report suggests this is not specific to Linux and because same
workaround works in U-boot simplified driver model I suggest you check
from your side.
Previously PCIe link training timeout, not working. Now I'm very happy
with working PCIe in Linux and U-boot.
Thanks,
Geraldo Nascimento
