On Wed, Nov 12, 2025 at 12:17:20PM +0530, Hrushikesh Salunke wrote: > This series adds PCIe endpoint boot support for the TI J784S4 SoC. > > PCIe boot allows the device to boot as a PCIe endpoint, where the > bootloader images are loaded by a PCIe host through Device Firmware > Upgrade (DFU) over PCIe. > > The J784S4 SoC uses PCIe1 instance with SERDES0 for endpoint boot. > To enable this functionality, the SERDES and PCIe peripherals must be > configured early in the R5 SPL stage before the bootloader images can > be transferred from the host. > > This series: > 1. Adds the required clock and device data for SERDES0 and PCIe1 > 2. Enables Cadence Torrent PHY driver at SPL stage > 3. Enables J721E WIZ SERDES wrapper driver at SPL stage > 4. Enables PCIe boot configs for R5 and A72 stage > > This feature has been tested on J784S4 EVM. Following are the logs > corresponding to this feature. > > https://gist.github.com/hrushikesh221/cf48b512eb4cd90c1612ad2e531b8ffe > > Program used to copy bootloaders from PCIe Root-Complex to Endpoint: > > https://gist.github.com/hrushikesh221/94e6042dbd717c74b74a5c9fc8ec5b6c > > This series is based on commit : > 6b27b688694 Merge branch 'master' of > https://source.denx.de/u-boot/custodians/u-boot-sh
This adds failure to build on am69_sk_r5 am69_sk_r5_ethboot j742s2_evm_r5 j784s4_evm_r5 on current next, thanks. -- Tom
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