It is been a while that the DDR ECC is missing. Pull from Altera trunk and sync to mainstream. Modifications are done to check ECC is on and only add necessary ECC code to SDRAM driver.
Signed-off-by: Brian Sune <[email protected]> --- drivers/ddr/altera/sdram_gen5.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 3c79bb11802..07d8087fc7e 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -19,6 +19,7 @@ #include <dm/device_compat.h> #include "sequencer.h" +#include "sdram_soc32.h" #ifdef CONFIG_XPL_BUILD @@ -562,6 +563,12 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) return temp; } +static int sdram_is_ecc_enabled(struct socfpga_sdr_ctrl *sdr_ctrl) +{ + return !!(readl(&sdr_ctrl->ctrl_cfg) & + SDR_CTRLGRP_CTRLCFG_ECCEN_MASK); +} + static int altera_gen5_sdram_of_to_plat(struct udevice *dev) { struct altera_gen5_sdram_plat *plat = dev_get_plat(dev); @@ -610,6 +617,14 @@ static int altera_gen5_sdram_probe(struct udevice *dev) goto failed; } + if (sdram_is_ecc_enabled(sdr_ctrl)) { + printf("DDR: ECC is enabled\n"); + /* Must set USEECCASDATA to 0 if ECC is enabled */ + clrbits_le32(&sdr_ctrl->static_cfg, + SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK); + sdram_init_ecc_bits(sdram_size); + } + priv->info.base = 0; priv->info.size = sdram_size; -- 2.34.1
