This patch series brings over several changes from Linux that are required to get PCIe working on the j722s and also enables PCIe in j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.
The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1 (using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes to the three drivers needed to be ported from Linux to enable the REFCLK output which is used with this SoC. These changes should be tested on other platforms using these drivers by those with the hardware available to make sure no problems were introduced. The PCIe controller in this SoC relies on the code performing the PCI scan not scanning devices which cannot exist. In Linux this is implemented as only_one_child() in probe.c. If this mechanism is not used, PCI config reads for subsequent functions will return information for device 0 resulting in U-Boot detecting 32 devices when only 1 is present. This change should be tested on other platforms with PCI to ensure the same PCI devices are enumerated before and after the patch is applied. I would like to thank Opto 22 for sponsoring the initial development and anyone that is able to contribute to testing of patches. George McCollister (6): pci: skip unnecessary PCIe scanning phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> phy: cadence-torrent: Add support to drive refclk out pci: pcie_cdns_ti: Add support to provide refclk to PCIe connector pci: pcie_cdns_ti: Add PCIe support for J722S SoC configs: j722s_evm_a53_defconfig: enable PCIe configs/j722s_evm_a53_defconfig | 8 ++ drivers/pci/pci-uclass.c | 32 +++++ drivers/pci/pcie_cdns_ti.c | 23 +++ drivers/phy/cadence/phy-cadence-torrent.c | 168 ++++++++++++++++++++++ drivers/phy/ti/phy-j721e-wiz.c | 46 ++++++ 5 files changed, 277 insertions(+) -- 2.51.2 base-commit: baf076aeb32dcdd2b022405088c3288ffc160fcf branch: j722s-pcie-next
