On Fri, Nov 14, 2025 at 12:08:03PM +0530, Balaji Selvanathan wrote: > Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 > clock driver. This clock is required for proper PHY operation > and eliminates clock-related warnings during USB initialization. > > Signed-off-by: Balaji Selvanathan <[email protected]> > --- > drivers/clk/qcom/clock-qcs615.c | 1 + > 1 file changed, 1 insertion(+)
Reviewed-by: Sumit Garg <[email protected]> -Sumit > > diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c > index 4700baba8c9..2b59c4d13fd 100644 > --- a/drivers/clk/qcom/clock-qcs615.c > +++ b/drivers/clk/qcom/clock-qcs615.c > @@ -66,6 +66,7 @@ static const struct gate_clk qcs615_clks[] = { > GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)), > GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), > GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), > + GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), > GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), > GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), > GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), > -- > 2.34.1 >
