Re: [PATCH v3 3/3] clk: stm32: Update clock management for STM32MP13/25

[Marek Vasut]

On 12/16/25 4:35 PM, Patrice CHOTARD wrote:

Hello Patrice,
sorry for the late reply.

        /* WWDG */
-       STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", "ck_icn_apb3", 0, GATE_WWDG1,
+       STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", IDX_ICN_APB3, 0, GATE_WWDG1,
                   SEC_RIFSC(103)),
-       STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", "ck_icn_ls_mcu", 0, 
GATE_WWDG2,
+       STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", IDX_ICN_LS_MCU, 0, 
GATE_WWDG2,
                   SEC_RIFSC(104)),
  };
  

Hi Marek

Can you give this patchset a try on DHCOR board in SPL ?
I have bad news, the SPL does not even start with this, no output on 
UART even. The problem seems to be in 3/3 , if I apply only 1/3 and 2/3 
the board does boot just fine.