This check is broken. r3 does not contain the silicon revision.
Signed-off-by: David Jander <da...@protonic.nl>
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 5 -----
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index ee4150d..f17d200 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -39,11 +39,6 @@
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
- cmp r3, #0x10 /* r3 contains the silicon rev */
-
- /* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
-
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
--
1.7.4.1
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