Devicetree clock references point at the main versaclock device. We
must determine the parent clock manually, as it depends on the clock id.
The device parent of the versaclock will generally be an I2C bus and not
another clock.
Fixes: dcf2cee77f2 ("clk: clk_versaclock: Add support for versaclock driver")
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/clk/clk_versaclock.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c
index 19a787eaf0c..7a1052a1be7 100644
--- a/drivers/clk/clk_versaclock.c
+++ b/drivers/clk/clk_versaclock.c
@@ -633,7 +633,15 @@ static unsigned long vc5_clk_out_set_rate(struct clk *hw,
unsigned long rate)
static unsigned long vc5_clk_out_get_rate(struct clk *hw)
{
- return clk_get_parent_rate(hw);
+ struct udevice *dev;
+ struct vc5_driver_data *vc;
+ struct clk *parent;
+
+ uclass_get_device_by_name(UCLASS_CLK, clk_hw_get_name(hw), &dev);
+ vc = dev_get_priv(dev);
+ parent = clk_get_parent(&vc->clk_out[hw->id].hw);
+
+ return clk_get_rate(parent);
}
static const struct clk_ops vc5_clk_out_ops = {
--
2.35.1.1320.gc452695387.dirty
