On Sun Jan 11, 2026 at 1:26 AM IST, Mark Kettenis wrote:
> Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> dcache_enable") broke Apple Silicon machines in certain scenarios.
> If the MMU is currently not enabled we need to flush the TLB
> before we enable it to prevent stale TLB entries from becoming
> active again. So move the __asm_invalidate_tlb_all() back
> immediately before the mmu_setup() call.
>
> Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
> Signed-off-by: Mark Kettenis <[email protected]>
> ---
> arch/arm/cpu/armv8/cache_v8.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 0309da6d397..39479df7b21 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned
> long stop)
> void dcache_enable(void)
> {
> /* The data cache is not active unless the mmu is enabled */
> - if (!mmu_status())
> + if (!mmu_status()) {
> + __asm_invalidate_tlb_all();
> mmu_setup();
So, if I understand correctly the problem is that the TLB is enabled by
mmu_setup which happened before we invalidated the existing TLB entries?
> + }
>
> /* Set up page tables only once (it is done also by mmu_setup()) */
> if (!gd->arch.tlb_fillptr)
> setup_all_pgtables();
>
> invalidate_dcache_all();
> - __asm_invalidate_tlb_all();
> set_sctlr(get_sctlr() | CR_C);
> }
>
