From: Raymond Mao <[email protected]> Enable clock nodes for K1 SoC in SPL.
Signed-off-by: Raymond Mao <[email protected]> --- arch/riscv/dts/k1-spl.dts | 51 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts index 6018ea1e452..1f6db740747 100644 --- a/arch/riscv/dts/k1-spl.dts +++ b/arch/riscv/dts/k1-spl.dts @@ -11,16 +11,63 @@ / { model = "spacemit k1 spl"; + aliases { + console = &uart0; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:115200n8"; bootph-all; }; }; +&vctcxo_1m { + status = "okay"; + bootph-pre-ram; +}; + +&vctcxo_24m { + status = "okay"; + bootph-pre-ram; +}; + +&vctcxo_3m { + status = "okay"; + bootph-pre-ram; +}; + +&osc_32k { + status = "okay"; + bootph-pre-ram; +}; + &soc { bootph-all; - serial@d4017000 { + system-controller@d4050000 { status = "okay"; - bootph-all; + bootph-pre-ram; + }; + clock-controller@d4090000 { + status = "okay"; + bootph-pre-ram; + }; + system-controller@d4282800 { + status = "okay"; + bootph-pre-ram; }; + system-controller@d4015000 { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, + <&vctcxo_24m>, <&syscon_mpmu CLK_PLL1_31P5>, + <&pll CLK_PLL1_D4>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", + "vctcxo_24m", "pll1_d78_31p5", "pll1_d4"; + status = "okay"; + bootph-pre-ram; + }; +}; + +&uart0 { + status = "okay"; + bootph-pre-ram; }; -- 2.25.1
