On Thu, Jan 22, 2026 at 03:44:04PM +0100, Francesco Dolcini wrote: > On Thu, Jan 22, 2026 at 07:38:38PM +0530, Anshul Dalal wrote: > > This patch refactors the nodes in each board's R5 device-tree to common > > SoC level dtsi. No functional change is intended from this patch. > > ... > > > diff --git a/arch/arm/dts/k3-am625-r5.dtsi b/arch/arm/dts/k3-am625-r5.dtsi > > new file mode 100644 > > index 00000000000..c509857ac5d > > --- /dev/null > > +++ b/arch/arm/dts/k3-am625-r5.dtsi > > @@ -0,0 +1,88 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ > > + */ > > + > > +/ { > > + aliases { > > + tick-timer = &main_timer0; > > + remoteproc0 = &sysctrler; > > + remoteproc1 = &a53_0; > > + serial0 = &wkup_uart0; > > + serial3 = &main_uart1; > > + }; > > + > > + a53_0: a53@0 { > > + compatible = "ti,am654-rproc"; > > + reg = <0x00 0x00a90000 0x00 0x10>; > > + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, > > + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, > > + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; > > + resets = <&k3_reset 135 0>; > > + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; > > + clock-names = "gtc", "core"; > > + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; > > + assigned-clock-parents = <&k3_clks 61 2>; > > + assigned-clock-rates = <200000000>, <1200000000>; > > + ti,sci = <&dmsc>; > > + ti,sci-proc-id = <32>; > > + ti,sci-host-id = <10>; > > + bootph-pre-ram; > > + }; > > .... > > > diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts > > b/arch/arm/dts/k3-am625-verdin-r5.dts > > index fb431c96337..dfd960aaf3c 100644 > > --- a/arch/arm/dts/k3-am625-verdin-r5.dts > > +++ b/arch/arm/dts/k3-am625-verdin-r5.dts > > @@ -9,75 +9,30 @@ > > #include "k3-am62-ddr.dtsi" > > > > #include "k3-am625-verdin-wifi-dev-u-boot.dtsi" > > +#include "k3-am625-r5.dtsi" > > > > / { > > - a53_0: a53@0 { > > - compatible = "ti,am654-rproc"; > > - reg = <0x00 0x00a90000 0x00 0x10>; > > - /* > > - * FIXME: Currently only the SPL running on the R5 has a clock > > - * driver. As a workaround therefore move the assigned-clock > > - * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio > > - * node of the regular device tree to here (last one each in > > - * below three lines, adding a <0> as spacing for parents). > > - */ > > - assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks > > 157 20>; > > - assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 > > 22>; > > - assigned-clock-rates = <200000000>, <800000000>, <25000000>; > ^^^^^^^^^^ > > Can you check this? On both verdin am62 and am62p? > > According to your diff nothing should change here, however if I look at > the code you are removing the ethernet clock.
Sorry, my fault. I see you are properly taking care of this, my fault. All good. Francesco
