Hi Brian,

On 27/1/2026 10:42 pm, Brian Sune wrote:
[CAUTION: This email is from outside your organization. Unless you trust the 
sender, do not click on links or open attachments as it may be a fraudulent 
email attempting to steal your information and/or compromise your computer.]

CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC550 C5 to mainstream u-boot
This is a more complex and unified board with
codec, WIFI feature. More info on [1]

[1]https://corecourse.cn/forum.php?mod=viewthread&tid=29788&extra=page%3D1

Signed-off-by: Brian Sune<[email protected]>
---
  arch/arm/dts/Makefile                         |   1 +
  arch/arm/dts/socfpga_cyclone5_ac550soc.dts    | 131 ++++
  .../dts/socfpga_cyclone_ac550soc-u-boot.dtsi  |  44 ++
  arch/arm/mach-socfpga/Kconfig                 |   7 +
  board/corecourse/ac550soc/MAINTAINERS         |   6 +
  board/corecourse/ac550soc/qts/iocsr_config.h  | 664 ++++++++++++++++++
  board/corecourse/ac550soc/qts/pinmux_config.h | 222 ++++++
  board/corecourse/ac550soc/qts/pll_config.h    |  86 +++
  board/corecourse/ac550soc/qts/sdram_config.h  | 349 +++++++++
  configs/socfpga_ac550soc_defconfig            |  85 +++
  include/configs/socfpga_ac550soc.h            |  13 +
  11 files changed, 1608 insertions(+)
  create mode 100644 arch/arm/dts/socfpga_cyclone5_ac550soc.dts
  create mode 100644 arch/arm/dts/socfpga_cyclone_ac550soc-u-boot.dtsi
  create mode 100644 board/corecourse/ac550soc/MAINTAINERS
  create mode 100644 board/corecourse/ac550soc/qts/iocsr_config.h
  create mode 100644 board/corecourse/ac550soc/qts/pinmux_config.h
  create mode 100644 board/corecourse/ac550soc/qts/pll_config.h
  create mode 100644 board/corecourse/ac550soc/qts/sdram_config.h
  create mode 100644 configs/socfpga_ac550soc_defconfig
  create mode 100644 include/configs/socfpga_ac550soc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2210b44f9bf..7ef9e9399cd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -470,6 +470,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               
\
         socfpga_cyclone5_sr1500.dtb                     \
         socfpga_cyclone5_vining_fpga.dtb                \
         socfpga_cyclone5_ac501soc.dtb                   \
+       socfpga_cyclone5_ac550soc.dtb                   \
         socfpga_n5x_socdk.dtb                           \
         socfpga_stratix10_socdk.dtb

diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc.dts 
b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts
new file mode 100644
index 00000000000..ea7744cff53
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025, Brian Sune
+ *
+ * based on socfpga_cyclone5_socdk.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+       model = "CoreCourse AC550SoC,AC802-CVA6";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+               stdout-path = "serial0:115200n8";
+       };
+
+       aliases {
+               ethernet0 = &gmac1;
+               udc0 = &usb1;
+       };
+
+       memory@0 {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x40000000>; /* 1GB */
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               hps0 {
+                       label = "hps_led0";
+                       gpios = <&portb 6 1>;
+               };
+
+               hps1 {
+                       label = "hps_led1";
+                       gpios = <&porta 9 1>;
+               };
+       };
+
+       buttons {
+               compatible = "gpio-keys";
+               hps0 {
+                       label = "HPS GPIO0";
+                       gpios = <&porta 0 0>;
+               };
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       clock-frequency = <100000>;
+};
+
+&i2c3 {
+       status = "okay";
+       clock-frequency = <100000>;
+
+       i2c-sda-falling-time-ns = <5000>;
+       i2c-scl-falling-time-ns = <5000>;
+
+       eeprom@50 {
+               compatible = "atmel,24c64";
+               reg = <0x50>;
+               pagesize = <32>;
+       };
+
+       rtc@51 {
+               compatible = "nxp,pcf8563";
+               reg = <0x51>;
+               #clock-cells = <0>;
+       };
+};
+
+&gmac1 {
+       status = "okay";
+       phy-mode = "rgmii";
+
+       rxd0-skew-ps = <420>;
+       rxd1-skew-ps = <420>;
+       rxd2-skew-ps = <420>;
+       rxd3-skew-ps = <420>;
+       txen-skew-ps = <0>;
+       txc-skew-ps = <1860>;
+       rxdv-skew-ps = <420>;
+       rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&porta {
+       bank-name = "porta";
+};
+
+&portb {
+       bank-name = "portb";
+};
+
+&portc {
+       bank-name = "portc";
+};
+
+&mmc0 {
+       status = "okay";
+       bootph-all;
+};
+
+&usb1 {
+       status = "okay";
+};
+
+&uart0 {
+       clock-frequency = <100000000>;
+       bootph-all;
+};
+
+&watchdog0 {
+       status = "disabled";
+};


Avoid duplicating nodes between the board DTS and the -u-boot.dtsi
(e.g., porta/portb/portc, watchdog0).

Keep board-common settings (usable by Linux and U-Boot) in the DTS;
U-Boot–specific bits belong in socfpga_cyclone_ac501soc-u-boot.dtsi.

bootph-all; is U-Boot-only and should be in the -u-boot.dtsi, not in the
DTS.

Thanks.

Best regards,

Tien Fong

Reply via email to