The DesignWare Cores Ethernet Quality-of-Service databook state that descriptors up to one location less than the one indicated by the descriptor tail pointer are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs:
Current Descriptor Pointer == Descriptor Tail Pointer The DMA goes into suspend mode when this condition occurs, and updating the tail pointer resume the DMA processing. Configure the transmit tail pointer to the first (current) descriptor pointer so that the tail pointer is a valid address instead of being initialized to NULL when transmit DMA is started. Also update the receive tail pointer comment to state that by pointing to the last descriptor we are actually implying that all receive descriptors are owned by and can be processed by the DMA. Signed-off-by: Jonas Karlman <[email protected]> --- drivers/net/dwc_eth_qos.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 74cdaa27644f..08332210afb4 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1011,12 +1011,17 @@ static int eqos_start(struct udevice *dev) setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); - /* TX tail pointer not written until we need to TX a packet */ /* - * Point RX tail pointer at last descriptor. Ideally, we'd point at the - * first descriptor, implying all descriptors were available. However, - * that's not distinguishable from none of the descriptors being - * available. + * Point TX tail pointer at the first descriptor, implying no descriptor + * are owned by the DMA. We advance the tail pointer when we need to TX + * a packet in eqos_send(). + */ + addr64 = (ulong)eqos_get_desc(eqos, 0, false); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_tail_pointer); + + /* + * Point RX tail pointer at the last descriptor, implying all + * descriptors are owned by the DMA. */ addr64 = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true); writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_tail_pointer); -- 2.52.0
