Hi Brian,
On 6/2/2026 11:09 pm, Sune Brian wrote:
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Hi Alif,
Since 2025.05 to the latest master.
I do not have any issue as you mentioned in this patch.
Both RD/WR are used on the FPGA2SDRAM SDRAM2FPGA.
I tested 256 AXI3 or split 128 AXI3 x2 which is the maximum
that GEN5 Cyclone can support.
Not too sure what is missing from first place?
Thanks,
Brian
Based on the CycloneV address map which can be found here -
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1411577374877.html.
Bit 3 of staticcfg register has to be set to apply all the settings
loaded in SDR registers to the memory interface, in this case the patch
ensures the SDRAM controller applies the latest configuration after
disabling FPGA SDRAM access.
This is a safety and correctness fix for re-initializing the memory
controller in the proper sequence during FPGA reconfiguration.
If you have the time, can you help to test this patch with your setup?
Although unlikely, we want to be sure that this patch will not break any
existing GEN5 boards out there.
Thanks,
Alif
