On Sun, Feb 15, 2026 at 03:58:35AM +0800, Sune Brian wrote: > On Sun, Feb 15, 2026 at 2:54 AM Tom Rini <[email protected]> wrote: > > > > On Sat, Feb 14, 2026 at 04:45:41AM +0000, Chee, Tien Fong wrote: > > > > > Dear Tom, > > > > > > This pull request updates SoCFPGA platforms with DDR improvements, new > > > board support, Agilex5 enhancements and general cleanup across the > > > codebase. > > > DDR and memory handling > > > > > > * > > > Add DRAM size checking support for Arria10. > > > * > > > Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver. > > > * > > > Assign unit address to memory node for improved memory representation and > > > consistency. > > > > > > Agilex / Agilex5 updates > > > > > > * > > > Restore multi-DTB support for NAND boot and fix NAND clock handling. > > > * > > > Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5. > > > * > > > Fix DT property naming conventions for Agilex5. > > > * > > > Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations to > > > avoid unintended clock control. > > > > > > New board support > > > > > > * > > > Add support for CoreCourse Cyclone V boards: > > > * > > > AC501 > > > * > > > AC550 > > > Including device trees, QTS configuration, defconfigs and maintainers > > > entries. > > > > > > Fixes and cleanup > > > > > > * > > > Fix GEN5 handoff script path. > > > * > > > Remove incorrect CONFIG_SPL_LDSCRIPT settings. > > > * > > > Replace legacy TARGET namespace and perform related cleanup across > > > SoCFPGA code. > > > * > > > General Kconfig, build and SoCFPGA maintenance updates. > > > > > > Overall this pull request improves platform robustness, adds new board > > > coverage and cleans up legacy configuration usage across the SoCFPGA > > > U-Boot codebase. > > > Thanks. > > > > > > Best regards, > > > Tien Fong > > > > > > The following changes since commit > > > f9ffeec4bdcf1da655a0ffea482062adde78fee8: > > > > > > board: toradex: Make A53 get RAM size from DT in K3 boards (2026-02-12 > > > 08:12:09 -0600) > > > > > > are available in the Git repository at: > > > > > > https://source.denx.de/u-boot/custodians/u-boot-socfpga.git > > > tags/u-boot-socfpga-next-20260213 > > > > > > for you to fetch changes up to 4b567f8e252e27f6dafdfe22de1bad147595e33b: > > > > > > Replace TARGET namespace and cleanup properly (2026-02-13 20:35:09 > > > +0800) > > > > > > > Hi Tom, > > Actually I am also troubled by this manners: > > If there are patches that are not committed yet while new patches do > rely on the other holding patches. > > Under that background should the new patch that relies on another > follow the new one or ignore the dependent patch. > Keep using the master to develop.
I'm not sure I follow you, sorry. It's hard to get gitlab to show the merge commit diff itself, but: $ git show 136faf7b0cc9 commit 136faf7b0cc92af1d38b0db1bfaa5405e884ee2d Merge: 6caff66ce469 62f7a9460209 Author: Tom Rini <[email protected]> Date: Sat Feb 14 08:58:38 2026 -0600 Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next This pull request updates SoCFPGA platforms with DDR improvements, new board support, Agilex5 enhancements and general cleanup across the codebase. DDR and memory handling * Add DRAM size checking support for Arria10. * Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver. * Assign unit address to memory node for improved memory representation and consistency. Agilex / Agilex5 updates * Restore multi-DTB support for NAND boot and fix NAND clock handling. * Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5. * Fix DT property naming conventions for Agilex5. * Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations to avoid unintended clock control. New board support * Add support for CoreCourse Cyclone V boards: * AC501 * AC550 Including device trees, QTS configuration, defconfigs and maintainers entries. Fixes and cleanup * Fix GEN5 handoff script path. * Remove incorrect CONFIG_SPL_LDSCRIPT settings. * Replace legacy TARGET namespace and perform related cleanup across SoCFPGA code. * General Kconfig, build and SoCFPGA maintenance updates. Overall this pull request improves platform robustness, adds new board coverage and cleans up legacy configuration usage across the SoCFPGA U-Boot codebase. [trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the new platforms this added] Signed-off-by: Tom Rini <[email protected]> diff --cc arch/arm/mach-socfpga/Kconfig index f2e959b56624,3a9e018ce234..aec0fb7b1c8e --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@@ -237,7 -237,15 +237,15 @@@ config TARGET_SOCFPGA_TERASIC_DE1_SO config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 + + config TARGET_SOCFPGA_CORECOURSE_AC501SOC + bool "CoreCourse AC501SoC (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 ++ select ARCH_SOCFPGA_CYCLONE5 + + config TARGET_SOCFPGA_CORECOURSE_AC550SOC + bool "CoreCourse AC550SoC (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 ++ select ARCH_SOCFPGA_CYCLONE5 endchoice And this is the simple and obviously correct type of change custodians are allowed to make, if they don't want to push changes out to being merged even later. The symbol TARGET_SOCFPGA_CYCLONE5 was globally renamed to ARCH_SOCFPGA_CYCLONE5, and so could have been corrected (And SoB'd) by Tien Fong. But since this didn't go through CI, it wasn't caught, so I fixed it up, rather than push everything back again. In some cases, people will develop their series and say it depends on another going in first, for example: https://patchwork.ozlabs.org/project/uboot/list/?series=489945 is functionally blocked by: https://patchwork.ozlabs.org/project/uboot/list/?series=491484 and the cover letter notes this. -- Tom
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