On 2/16/2026 3:58 PM, Siddharth Vadapalli wrote:
From: Hrushikesh Salunke <[email protected]>
To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled
and configured at the R5 stage. Add the required clk-data and dev-data
for SERDES0 and PCIE1.
Signed-off-by: Hrushikesh Salunke <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
arch/arm/mach-k3/r5/j784s4/clk-data.c | 184 ++++++++++++++++++++++++--
arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 ++++---
2 files changed, 201 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c
b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 24780eb6562..228b424d3f2 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <[email protected]>.
*
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
*/
Reviewed-by: Udit Kumar <[email protected]>
#include <linux/clk-provider.h>
[..]
