The a53_0 clock properties are already set correctly in their
common k3-<soc>-r5.dtsi includes. Stop overriding them in
the r5 board device trees.

Fixes the following error message:
  Failed to set clock rates for '/a53@0': -61

Signed-off-by: Wadim Egorov <[email protected]>
---
 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts  | 5 -----
 arch/arm/dts/k3-am625-verdin-r5.dts           | 1 -
 arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts | 5 -----
 arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts  | 5 -----
 4 files changed, 16 deletions(-)

diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts 
b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
index 46b621242b5..ac6f1022a55 100644
--- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
+++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
@@ -21,11 +21,6 @@
        };
 };
 
-&a53_0 {
-       clock-names = "gtc";
-       clocks = <&k3_clks 61 0>;
-};
-
 &main_pktdma {
        ti,sci = <&dm_tifs>;
 };
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts 
b/arch/arm/dts/k3-am625-verdin-r5.dts
index dfd960aaf3c..971bb752052 100644
--- a/arch/arm/dts/k3-am625-verdin-r5.dts
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -24,7 +24,6 @@
 };
 
 &a53_0 {
-       clocks = <&k3_clks 61 0>;
        /*
         * FIXME: Currently only the SPL running on the R5 has a clock
         * driver. As a workaround therefore move the assigned-clock
diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts 
b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
index b54cd9d48a4..c949485017e 100644
--- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
+++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
@@ -22,11 +22,6 @@
        };
 };
 
-&a53_0 {
-       clocks = <&k3_clks 61 0>;
-       clock-names = "gtc";
-};
-
 &cbass_main {
        bootph-pre-ram;
        sa3_secproxy: secproxy@44880000 {
diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts 
b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
index 4b7a63db4ce..6f3a2628353 100644
--- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
+++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
@@ -21,8 +21,3 @@
                ethernet0 = &cpsw3g;
        };
 };
-
-&a53_0 {
-       clock-names = "gtc";
-       clocks = <&k3_clks 61 0>;
-};
-- 
2.48.1

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