On Fri, Dec 05, 2025 at 03:21:05AM +0000, Jeffrey Yu wrote: > Signed-off-by: jeffrey yu <[email protected]> > --- > drivers/mtd/spi/spi-nor-ids.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index b4221a82e01..c6d65196ebc 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -222,6 +222,8 @@ const struct flash_info spi_nor_ids[] = { > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_TB) }, > { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25lp512mj", 0x9d6020, 0, 64 * 1024, 1024, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > { INFO("is25lp02g", 0x9d6022, 0, 64 * 1024, 4096, > @@ -239,6 +241,8 @@ const struct flash_info spi_nor_ids[] = { > SPI_NOR_4B_OPCODES) }, > { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("is25wp512mj", 0x9d7020, 0, 64 * 1024, 1024, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, > @@ -249,6 +253,22 @@ const struct flash_info spi_nor_ids[] = { > SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, > { INFO("is25lp01gg", 0x9d6021, 0, 64 * 1024, 2048, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25lp010e", 0x9d4011, 0, 64 * 1024, 2, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("is25lp020e", 0x9d4012, 0, 64 * 1024, 4, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("is25lp040e", 0x9d4013, 0, 64 * 1024, 8, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO("is25lp01gj", 0x9d6021, 0, 64 * 1024, 2048, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25lp02gg", 0x9d6022, 0, 64 * 1024, 4096, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25lp02gj", 0x9d6022, 0, 64 * 1024, 4096, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25wp01gg", 0x9d7021, 0, 64 * 1024, 2048, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25wp01gj", 0x9d7021, 0, 64 * 1024, 2048, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25wj128f", 0x9d7118, 0, 64 * 1024, 256, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25wp02gg", 0x9d7022, 0, 64 * 1024, 4096, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > + { INFO("is25wp02gj", 0x9d7022, 0, 64 * 1024, 4096, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_HAS_TB) }, > #endif > #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ > /* Macronix */
In that this introduces no new problems with how we handle these types of flash today, this is OK. However, the commit subject needs to be clarified and then an actual commit message needs to be provided, perhaps with some links to datasheets or similar. Thanks. -- Tom
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