On Mon, 23 Feb 2026 at 23:23, Mark Kettenis <[email protected]> wrote: > > > Hi Mark, > > Hi Ilias, > > Sorry for the late reply. I was a bit busy the last weeks... > > > On Sat, 10 Jan 2026 at 21:56, Mark Kettenis <[email protected]> wrote: > > > > > > Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on > > > dcache_enable") broke Apple Silicon machines in certain scenarios. > > > If the MMU is currently not enabled we need to flush the TLB > > > before we enable it to prevent stale TLB entries from becoming > > > active again. So move the __asm_invalidate_tlb_all() back > > > immediately before the mmu_setup() call. > > > > > > Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on > > > dcache_enable") > > > Signed-off-by: Mark Kettenis <[email protected]> > > > --- > > > > Should we keep the check here or mayber move it in mmu_setup()? > > It would make sense to move it to mmu_setup(), but I went for a > partial revert as there is an alternative implementation of > mmu_setup() in cpu/armv8/fsl-layerscape/cpu.c and I couldn't test that > code. > > Hope this can still make the next release.
Ok that's unfortunate. Let's get it in now since it's a fix Reviewed-by: Ilias Apalodimas <[email protected]> > > > Thanks > > /Ilias > > > > > arch/arm/cpu/armv8/cache_v8.c | 5 +++-- > > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c > > > index 0309da6d397..39479df7b21 100644 > > > --- a/arch/arm/cpu/armv8/cache_v8.c > > > +++ b/arch/arm/cpu/armv8/cache_v8.c > > > @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, > > > unsigned long stop) > > > void dcache_enable(void) > > > { > > > /* The data cache is not active unless the mmu is enabled */ > > > - if (!mmu_status()) > > > + if (!mmu_status()) { > > > + __asm_invalidate_tlb_all(); > > > mmu_setup(); > > > + } > > > > > > /* Set up page tables only once (it is done also by mmu_setup()) > > > */ > > > if (!gd->arch.tlb_fillptr) > > > setup_all_pgtables(); > > > > > > invalidate_dcache_all(); > > > - __asm_invalidate_tlb_all(); > > > set_sctlr(get_sctlr() | CR_C); > > > }
