From: Padmarao Begari <[email protected]> The Zynq GEM TX status register retains the transfer‑complete bit until it is explicitly cleared. The current flow waits for transfer‑complete but never clears it, so on the next send the wait loop returns immediately because transfer‑complete is already high. This causes the driver to report TX completion before the new DMA transfer has actually finished, which breaks back‑to‑back transmissions. This issue causes timeouts during LWIP TFTP transfers when cache coherency is enabled. Fix this by explicitly clearing transfer‑complete (write‑to‑clear) after the wait completes, so each transmit starts with a clean TXSR.
Co-developed-by: Harini Katakam <[email protected]> Signed-off-by: Harini Katakam <[email protected]> Co-developed-by: Michal Simek <[email protected]> Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Padmarao Begari <[email protected]> Message-ID: <[email protected]> --- drivers/net/zynq_gem.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b05c752b17eb..41883a440528 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -693,6 +693,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { dma_addr_t addr; u32 size; + int ret; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; @@ -734,8 +735,13 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) printf("TX buffers exhausted in mid frame\n"); - return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000, true); + ret = wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000, true); + + /* Clear the transfer complete */ + setbits_le32(®s->txsr, ZYNQ_GEM_TSR_DONE); + + return ret; } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ -- 2.43.0
