From: Emanuele Ghidoli <[email protected]> Move the existing 16GB single-rank configuration to HW_CFG 0x03 and use the previous HW_CFG 0x01 value for the new 16GB dual-rank configuration.
There is no hardware using the former 16GB single-rank configuration, so reuse the HW_CFG value for the new 16GB dual-rank configuration, which will be used in production. Signed-off-by: Emanuele Ghidoli <[email protected]> --- board/toradex/aquila-am69/Makefile | 1 + board/toradex/aquila-am69/aquila-am69.c | 8 ++- board/toradex/aquila-am69/aquila_ddrs.h | 1 + .../aquila-am69/aquila_ddrs_16GB_rank_2.c | 54 +++++++++++++++++++ 4 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c diff --git a/board/toradex/aquila-am69/Makefile b/board/toradex/aquila-am69/Makefile index aa71c4bbb210..aa657ac8a420 100644 --- a/board/toradex/aquila-am69/Makefile +++ b/board/toradex/aquila-am69/Makefile @@ -6,4 +6,5 @@ obj-y += aquila-am69.o obj-y += ddrs_patch.o obj-y += aquila_ddrs_16GB.o +obj-y += aquila_ddrs_16GB_rank_2.o obj-y += aquila_ddrs_8GB.o diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index c3df14fc7c96..0c7123a059e4 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -23,8 +23,9 @@ #define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4 #define HW_CFG_MEM_SZ_32GB 0x00 -#define HW_CFG_MEM_SZ_16GB 0x01 +#define HW_CFG_MEM_SZ_16GB_RANK_2 0x01 #define HW_CFG_MEM_SZ_8GB 0x02 +#define HW_CFG_MEM_SZ_16GB 0x03 #define HW_CFG_MEM_CFG_MASK 0x03 @@ -41,6 +42,7 @@ static u64 aquila_am69_memory_size(void) switch (aquila_am69_memory_cfg()) { case HW_CFG_MEM_SZ_32GB: return SZ_32G; + case HW_CFG_MEM_SZ_16GB_RANK_2: case HW_CFG_MEM_SZ_16GB: return SZ_16G; case HW_CFG_MEM_SZ_8GB: @@ -88,6 +90,10 @@ static void update_ddr_timings(void) ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB, MULTI_DDR_CFG_INTRLV_SIZE_8GB); break; + case HW_CFG_MEM_SZ_16GB_RANK_2: + ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB_rank_2, + MULTI_DDR_CFG_INTRLV_SIZE_16GB); + break; case HW_CFG_MEM_SZ_16GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB, MULTI_DDR_CFG_INTRLV_SIZE_16GB); diff --git a/board/toradex/aquila-am69/aquila_ddrs.h b/board/toradex/aquila-am69/aquila_ddrs.h index 3f6cecf5405f..7a58be3fd299 100644 --- a/board/toradex/aquila-am69/aquila_ddrs.h +++ b/board/toradex/aquila-am69/aquila_ddrs.h @@ -10,5 +10,6 @@ extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4]; extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4]; +extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4]; #endif // __AQUILA_DDRS_H diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c new file mode 100644 index 000000000000..c24e22b620b5 --- /dev/null +++ b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) Toradex - https://www.toradex.com/ + * This contains a diff against the 32GB register settings created from + * the 16GB dual rank tool output. + + * The 16GB dtsi file was generated with the following tool revisions: + * - SysConfig: Revision 1.26.2+4477 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Fri Mar 06 2026 10:39:50 GMT+0100 (Central European Standard Time) + */ + +#include <asm/u-boot.h> +#include <linux/kernel.h> +#include "ddrs_patch.h" + +#define DDRSS_PLL_FHS_CNT 3 + +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF + +#define DDRSS_PI_73_DATA 0x00080100 + +static struct ddr_reg_patch ctl_patch[] = { + { 268, DDRSS_CTL_268_DATA}, + { 270, DDRSS_CTL_270_DATA}, + { 271, DDRSS_CTL_271_DATA}, + { 272, DDRSS_CTL_272_DATA}, + { 273, DDRSS_CTL_273_DATA} +}; + +static struct ddr_reg_patch pi_patch[] = { + { 73, DDRSS_PI_73_DATA}, +}; + +static struct ddrss_patch ddrss_ctrl_patch = { + .ddr_fhs_cnt = DDRSS_PLL_FHS_CNT, + .ctl_patch = ctl_patch, + .ctl_patch_num = ARRAY_SIZE(ctl_patch), + .pi_patch = pi_patch, + .pi_patch_num = ARRAY_SIZE(pi_patch), + .phy_patch = NULL, + .phy_patch_num = 0 +}; + +struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4] = { + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch +}; -- 2.43.0
