Le 09/03/2026 à 16:22, Richard Genoud a écrit :
In Allwinner SoCs, user data can be added in OOB before each ECC data. For older SoCs like A10, the user data size was the size of a register (4 bytes) and was mandatory before each ECC step. So, the A10 OOB Layout is: [4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [4bytes USER_DATA_STEP1] [ECC_STEP1 bytes] ... NB: the BBM is stored at the beginning of the USER_DATA_STEP0.Now, for H6/H616 NAND flash controller, this user data can have a different size for each step. And the vendor has chosen a different layout from the one on A10, using 8 bytes for step 0 and nothing for further steps: [8bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [ECC_STEP1 bytes]... (Still with BBM stored at the beginning of the USER_DATA_STEP0) In order to be compatible with this layout, the current one for H6/H616 has to be changed. Fixes: 7d1de9801151 ("mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller") Fixes: f163da5e6d26 ("mtd: rawnand: sunxi: add support for H6/H616 nand controller") Signed-off-by: Richard Genoud <[email protected]>
On Linux ML, it was asked to maximize the user data length instead of relying on vendor OOB layout, so I'll send a v2 with the same behavior. cf: https://lore.kernel.org/lkml/[email protected]/ Regards, Richard
