> -----Original Message----- > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > Sent: Thursday, July 21, 2011 11:10 AM > To: Prafulla Wadaskar > Cc: u-boot@lists.denx.de; Ajay Bhargav > Subject: [PATCH 2/2] gpio: Add GPIO driver for Marvell SoC Armada100 > > This patch adds support for generic GPIO driver framework for Marvell > SoC Armada100. > > Signed-off-by: Ajay Bhargav <ajay.bhar...@einfochips.com> > --- > arch/arm/include/asm/arch-armada100/gpio.h | 71 > ++++++++++++++++++++++++++++ > 1 files changed, 71 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h > > diff --git a/arch/arm/include/asm/arch-armada100/gpio.h > b/arch/arm/include/asm/arch-armada100/gpio.h > new file mode 100644 > index 0000000..4dd0179 > --- /dev/null > +++ b/arch/arm/include/asm/arch-armada100/gpio.h > @@ -0,0 +1,71 @@ > +/* > + * (C) Copyright 2011 > + * eInfochips Ltd. <www.einfochips.com> > + * Written-by: Ajay Bhargav <ajay.bhar...@einfochips.com> > + * > + * (C) Copyright 2010 > + * Marvell Semiconductor <www.marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301 USA > + */ > + > +#ifndef _ASM_ARCH_GPIO_H > +#define _ASM_ARCH_GPIO_H > + > +#include <mvgpio.h>
Remove this include. > + > +/* > + * GPIO register map > + * Refer Datasheet Appendix A.36 > + */ > +struct gpio_reg { > + u32 gplr; /* Pin Level Register */ It is good if you also mention register offset in comment field as it was there earlier. It helps to keep track with documentation. > + u32 pad0[2]; > + u32 gpdr; /* Pin Direction Register */ > + u32 pad1[2]; > + u32 gpsr; /* Pin Output Set Register */ > + u32 pad2[2]; > + u32 gpcr; /* Pin Output Clear Register */ > + u32 pad3[2]; > + u32 grer; /* Rising-Edge Detect Enable Register */ > + u32 pad4[2]; > + u32 gfer; /* Falling-Edge Detect Enable Register */ > + u32 pad5[2]; > + u32 gedr; /* Edge Detect Status Register */ > + u32 pad6[2]; > + u32 gsdr; /* Bitwise Set of GPIO Direction Register */ > + u32 pad7[2]; > + u32 gcdr; /* Bitwise Clear of GPIO Direction Register */ > + u32 pad8[2]; > + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable > + Register */ > + u32 pad9[2]; > + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable > + Register */ > + u32 pad10[2]; > + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable > + Register */ > + u32 pad11[2]; > + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable > + Register */ > + u32 pad12[2]; > + u32 apmask; /* Bitwise Mask of Edge Detect Register */ > +}; > + > +#endif /* _ASM_ARCH_GPIO_H */ > -- > 1.7.0.4 Regards.. Prafulla . . _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot