After DMA transfer, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu <hong...@atmel.com>
Tested-by: Elen Song <elen.s...@atmel.com>
CC: Heiko Schocher <h...@denx.de>
CC: Albert Aribaud <albert.arib...@free.fr>
---
arch/arm/lib/cache.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..216bde0 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,13 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+ return;
+}
+void invalidate_dcache_all(void)
+ __attribute__((weak, alias("__invalidate_dcache_all")));
--
1.7.3.3
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