Add i2c registers for Freescale imx1/L/S Signed-off-by: Eric Jarrige <eric.jarr...@armadeus.org> Cc: Stefano Babic <sba...@denx.de> --- arch/arm/include/asm/arch-imx/imx-regs.h | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h index 0c26a36..a7b3404 100644 --- a/arch/arm/include/asm/arch-imx/imx-regs.h +++ b/arch/arm/include/asm/arch-imx/imx-regs.h @@ -638,4 +638,27 @@ extern void imx_gpio_mode(int gpio_mode); #define TSTAT_CAPT (1<<1) /* Capture event */ #define TSTAT_COMP (1) /* Compare event */ +/* + * I2C module + */ +#define IADR __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */ +#define IFDR __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/ +#define I2CR __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */ +#define I2SR __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */ +#define I2DR __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */ +/* I2C Control Register Bit Fields */ +#define I2CR_IEN (1<<7) /* I2C Enable */ +#define I2CR_IIEN (1<<6) /* I2C Interrupt Enable */ +#define I2CR_MSTA (1<<5) /* I2C Master/Slave Mode Select */ +#define I2CR_MTX (1<<4) /* I2C Transmit/Receive Mode Select */ +#define I2CR_TXAK (1<<3) /* I2C Transmit Acknowledge Enable */ +#define I2CR_RSTA (1<<2) /* I2C Repeated START */ +#define I2SR_ICF (1<<7) /* I2C Data Transfer */ +#define I2SR_IAAS (1<<6) /* I2C Addressed As a Slave */ +#define I2SR_IBB (1<<5) /* I2C Bus Busy */ +#define I2SR_IAL (1<<4) /* I2C Arbitration Lost */ +#define I2SR_SRW (1<<2) /* I2C Slave Read/Write */ +#define I2SR_IIF (1<<1) /* I2C interrupt */ +#define I2SR_RXAK (1<<0) /* I2C Received Acknowledge */ + #endif /* _IMX_REGS_H */ _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
