Marvell 88SV331xV5 has its specific arm cp15 opcode, which could
flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen <lei...@marvell.com>
---
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 2d9c13a..8f94ea9 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -105,3 +105,17 @@ void i2c_clk_enable(void)
{
}
#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ /* clean & invalidate all D cache */
+ asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+}
+#endif
--
1.7.0.4
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