On Mon, Sep 26, 2011 at 04:02:30PM +0000, Laurence Withers wrote: > In nand_davinci_readecc(), select the correct NANDF<n>ECC register based > on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. > This allows 1-bit hardware ECC to work with chip select other than CS2. > > Note this now matches the usage in nand_davinci_enable_hwecc(), which > already had the correct handling, and allows refactoring to a single > function encapsulating the register read. > > Without this fix, writing NAND pages to a chip not wired to CS2 would > result in in the ECC calculation always returning FFFFFF for each > 512-byte segment, and reading back a correctly written page (one with > ECC intact) would always fail. With this fix, the ECC is written and > verified correctly. > > Signed-off-by: Laurence Withers <lwith...@guralp.com>
Does anybody have any comments on this bugfix? If not, can it be accepted? Many thanks, and bye for now, -- Laurence Withers, <lwith...@guralp.com> http://www.guralp.com/ Direct tel:+447753988197 or tel:+443333408643 Software Engineer General support queries: <supp...@guralp.com> CMG-DCM CMG-EAM CMG-NAM _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
